https://github.com/dlwotjr/HDL_Bits
GitHub - dlwotjr/HDL_Bits
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https://hdlbits.01xz.net/wiki/Main_Page
HDLBits
HDLBits — Verilog Practice HDLBits is a collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL). Earlier problems follow a tutorial style, while later problems will increasingl
hdlbits.01xz.net
0-1. 문제 : Step one
module top_module( output one );
// Insert your code here
assign one = 1;
endmodule
//동일한 코드로 이렇게도 됨
module top_module( output one );
assign one = 1'b1;
//처음의 1 : 비트 수 지정
//`b : 이진법임
// 1 : 숫자 1
endmodule
0-2. 문제 : output Zero
module top_module(
output zero
);// Module body starts after semicolon
assign zero = 1'b0;//사실 처음에 0으로 초기화 되어있어서 아무것도 안써도 됨
endmodule
