HDLBits (Circuits - Combinational Logic - MUX) - Verilog 문제 풀이 2-1-2

https://github.com/dlwotjr/HDL_Bits

GitHub - dlwotjr/HDL_Bits

https://hdlbits.01xz.net/wiki/Mux256to1v

Mux256to1v - HDLBits

 

 

문제 : 2:1MUX

module top_module(
    input a, b, sel,
    output out
); 
    assign out = (sel == 1) ? b : a;

endmodule

문제 :2:1 bus MUX

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    assign out = (sel ==1)?b:a;
endmodule

문제 : 9:1 MUX

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );

   always @(*) begin
        case (sel)
            4'b0000: out = a; 
            4'b0001: out = b; 
            4'b0010: out = c; 
            4'b0011: out = d;
            4'b0100: out = e;
            4'b0101: out = f;
            4'b0110: out = g;
            4'b0111: out = h;
            4'b1000: out = i;
            default: out = 16'hffff; 
        endcase
    end

endmodule

문제 : 256 :1 MUX

module top_module(
    input [255:0] in,
    input [7:0] sel,
    output out
);

    assign out = in[sel];

endmodule

문제 : 156:1 4-bit MUX

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out
);

    assign out = in[sel*4 +: 4]; // Part-select를 사용하여 4비트 값을 선택

endmodule