HDLBits (Verilog Language - More Verilog Features) - Verilog 문제 풀이 1-5

https://github.com/dlwotjr/HDL_Bits

GitHub - dlwotjr/HDL_Bits

https://hdlbits.01xz.net/wiki/Main_Page

HDLBits

 

Conditional Ternary Operatior

• 삼항 연산자 (condition ? if_true : if_false)Example
• 2:1MUX , TFF, one input FSM, tri-state buffer(3:1MUX)

(0 ? 3 : 5)     // This is 5 because the condition is false.
(sel ? b : a)   // A 2-to-1 multiplexer between a and b selected by sel.

always @(posedge clk)         // A T-flip-flop.
  q <= toggle ? ~q : q;

always @(*)                   // State transition logic for a one-input FSM
  case (state)
    A: next = w ? B : A;
    B: next = w ? A : B;
  endcase

assign out = ena ? q : 1'bz;  // A tri-state buffer

((sel[1:0] == 2'h0) ? a :     // A 3-to-1 mux
 (sel[1:0] == 2'h1) ? b :
                      c )

 

 

 

 

 

문제 : Conditional ternary operator

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    wire [7:0] temp_result1, temp_result2;
    assign temp_result1 = a<b? a:b;
    assign temp_result2 = temp_result1<c? temp_result1:c;
    assign min = temp_result2<d? temp_result2:d;
    //assign out = temp_result1;

endmodule

 

 

 

 

 

문제 : Reduction

• Bit operator vector calculate by once
• & a[3:0] // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4'hf)
• | b[3:0] // OR: b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4'h0)
• ^ c[2:0] // XOR: c[2]^c[1]^c[0]

module top_module (
    input [7:0] in,
    output parity); 
    assign parity = ^in[7:0];
endmodule

 

 

 

 

 

문제 : Reduction Even_wider_Gates

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    assign out_and = &in[99:0];
    assign out_or = |in[99:0];
    assign out_xor = ^in[99:0];
endmodule

 

 

 

 

 

문제 : Comginational for-loop Vector reversal2

• 2가지 풀이법
• generate 사용
  • 내부에서 assign문을 사용할 때 사용
  • genvar를 통해서 루프 변수 생성
  • generate / endgenerate 사용해 for 루프 포함
• always 사용
  • integer i를 이용해 정수형 변수 생성

module top_module(
    input [99:0] in,
    output [99:0] out
);

    genvar i;
    generate
        for (i = 0; i < 100; i = i + 1) begin : bit_reverse
            assign out[99-i] = in[i];
        end
    endgenerate

endmodule


module top_module(
    input [99:0] in,
    output reg [99:0] out
);
    always @(*) begin
        integer i;
        for (i = 0; i < 100; i = i + 1) begin
            out[99 - i] = in[i];
        end
    end
endmodule

 

 

 

 

 

문제 : Combinational for-loop : Popcont255

module top_module( 
    input [254:0] in,
    output [7:0] out );

    always @(*) begin
        integer i;
        out =0;
        for (i = 0; i < 255; i = i + 1) begin
            out = out + in[i];
        end
    end

endmodule

 

 

 

 

 

문제 : Generate for-loop :100-bit binary adder2

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    genvar i;
    full_adder ins1(a[0],b[0],cin,sum[0],cout[0]);
    generate
        for(i=1;i<100;i++)begin : full_adder
            full_adder ins(a[i],b[i],cout[i-1],sum[i],cout[i]);
        end
    endgenerate
endmodule

module full_adder(input a,b,cin, output sum, cout);
    assign sum = a^b^cin;
    assign cout = (a&b)|(b&cin)|(a&cin);    
endmodule

 

 

 

 

 

문제 : Generate for-loop:100-degit-BCD adder

• carry를 단일 wire로 사용시 계속 재사용하면 안됨 - generate블록 내부에서 같은 인자 재사용하면 안됨

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );

    wire [100:0] carry; 

    genvar i;
    assign carry[0] = cin; 

    bcd_fadd ins1(a[3:0], b[3:0], carry[0], carry[1], sum[3:0]);

    generate
        for(i = 1; i < 100; i++) begin: bcd_fadd_block
            bcd_fadd ins(a[4*i+3:4*i], b[4*i+3:4*i], carry[i], carry[i+1], sum[4*i+3:4*i]);
        end
    endgenerate

    assign cout = carry[100]; 

endmodule

//틀린코드
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );

    wire carry1, carry2;  // 문제 발생 원인

    genvar i;
    bcd_fadd ins1(a[3:0], b[3:0], cin, carry1, sum[3:0]);

    generate
        for(i = 1; i < 100; i++) begin : bcd_fadd 
            bcd_fadd ins(a[4*i+3:4*i], b[4*i+3:4*i], carry1, carry2, sum[4*i+3:4*i]);
            assign carry1 = carry2;  // 할당 방식 문제
        end
    endgenerate

    assign cout = carry1;
endmodule